This invention relates to a digital data processing system, and more particularly, to an apparatus for dynamically switching the clock source of a computer system without causing the computer system to experience any malfunction or error in its currently operating task, i.e., without interrupting the data processing system.
In current data processing systems which include more than one central system, each central system has a clock or timing subsystem, the clock of each central system providing the clocking signals (or timing signals) to the subsystems associated with its central system. When it is necessary or desirous to have the two central systems synchronized, the timing signals of the two central systems are synchronized by utilizing a phase locked-loop circuit. In this manner, the equipments or subsystems of each central system are operating from synchronized clocks.
In the present invention each central system has a corresponding timing subsystem; however, the clocking signal generated from one of the timing subsystems provides the clocking signal for both central systems. If it is desirous or necessary to switch the source of the clocking signal from the timing subsystem of the currently active timing subsystem to the currently passive timing subsystem, the apparatus of the present invention will permit the switching of the clocking signals source to occur without interrupting the running of the subsystems of the central systems.